1. Technical Field
The invention concerns a complementary bipolar semiconductor device, hereinafter also referred to as a CBi semiconductor device, comprising a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. The invention further concerns a process for the production of such a complementary bipolar semiconductor device.
The present application fully incorporates German patent application No DE 103 58 047.6 of 5.12.1003, the priority of which is claimed, in the sense of an ‘Incorporation by Reference’ in pursuance of American law.
2. Discussion of Related Art
The operational efficiency of bipolar transistors (also referred to in English as a bipolar junction transistor or BJT) on a silicon base has been substantially improved in the high-speed area by the use of a heterobase layer which is produced by means of epitaxy. A further impetus in terms of power has been implemented in the case of npn-heterobipolar transistors (HBTs) by the additional incorporation of carbon into a boron-doped base of silicon-germanium (SiGe).
For reasons relating to circuitry engineering it is often advantageous to have npn- and pnp-transistors on a chip at the same time.
In addition integration with complementary metal oxide semiconductor (CMOS) transistors can also afford additional advantages.
Essential features of a high-speed bipolar transistor with an epitaxial base, which can be inexpensively produced, are set forth in WO 03/046948 A2. The transistor described therein permits in particular simplified integration either of an npn- or a pnp-high-speed HBT in CMOS technology. Such technology is referred to as BiCMOS technology. It is not possible to see from WO 03/046948 A2 however how npn- and pnp-transistors can be integrated jointly in a CBi conductor device.
In the case of pnp-heterobipolar transistors (pnp-HBTs) which operate in the high-speed range, the advances in past years have been rather slight in comparison with the advances in terms of further development of npn-HBTs, in particular npn-SiGe-HBTs. The following reasons are primarily to be named for those slight advances in improvement in the high-speed properties of pnp-HBTs:
a) Good high frequency properties in the case of npn-transistors fit in with the type of the heterojunction of Si/SiGe, while that kind of heterojunction can adversely affect the operational efficiency of pnp-transistors, see D V Singh, J L Hoyt and J F Gibbons: ‘Novel epitaxial p-Si/n-Si1-yCy/p-Si heterojunction bipolar transistors’, IEDM 2000, pages 749-752 or D V Singh, J L Hoyt and J F Gibbons: ‘Effect of band alignment and density of states on the collector current in p-Si/n-Si1-yCy/p-SiHBTs’, IEEE Trans. Electron. Devices, Vol 50, pages 425-432, February 2003.
b) By virtue of the deposit and diffusion properties of the respective dopants, the demands on the doping profile of npn-high-speed transistors can be more easily satisfied in a BiCMOS process, than those for a pnp-transistor.
c) The process complexity of conventional complementary bipolar or BiCMOS processes is so great and the mutual influence of the process modules on device parameters is so considerable that there are few approaches which aim at an improvement in the high frequency properties of pnp-transistors in a CBIMOS semiconductor device.
Design features, corresponding to the present day state of the art, in respect of complementary bipolar transistors and process steps of a complementary SiGe-BiCMOS technology are published in B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C. Dirnecker, P Foglietti, A Haesler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M Waitschull, J W Weijtmans and C Willis: ‘A 5V complementary-SiGe BiCMOS technology for high-speed precision analog circuits’, BCTM pages 211-24, 2003 (hereinafter El-Kareh et al). The solution described therein aims at lowest possible parasitic capacitances and a collector resistance which is as low as possible.
Small collector substrate capacitances are implemented by means of deep trenches filled with insulator material and with a buried oxide layer using SOI technology (‘silicon on insulator’). In addition the buried oxide layer in conjunction with the deep trenches ensures electrical insulation of the collectors in relation to the substrate. In order to keep down the collector resistances, El-Kareh et al use epitaxially buried, highly doped collector layers and special implantation steps for a low-ohmic connection of the buried collector layers, referred to as ‘collector sinkers’. El-Kareh et al, with that technology, attain limit frequencies fT/fmax of 19/60 GHz for npn-transistors and 19/45 GHz for pnp-transistors.
A disadvantage of that process however is that typical modern CMOS technologies do not include either epitaxially buried collector layers or deep insulation trenches or collector sinkers. The process expenditure for those process steps is in part considerable. As the CMOS transistors are introduced into the epitaxy layer which is deposited over the buried collector layers, an additional heat loading of the buried collector layers used by El-Kareh et al during the CMOS process cannot be avoided. That reduces the profile gradient of the buried collector layers, whereby the efficiency of both bipolar transistor types but in particular that of the pnp-transistors in the high-speed range is adversely affected.
Furthermore the process described by El-Kareh et al suffers from the disadvantage that process steps for CMOS and bipolar devices are coupled. Thus, a gate polysilicon layer stack is produced, which results from two polysilicon deposit operations. The second polysilicon layer is produced during deposit of the base of the npn-bipolar transistors in the form of a p-doped polycrystalline SiGe layer. That is intended to pursue the aim of keeping down the level of process complication and expenditure and thus the complexity and cost of the proposed complementary BiCMOS technology. The disadvantage of that process however is that the interchangeability, which is usually an aim to strive for, of process modules, for example the replacement of an aged CMOS generation by a fresh one, is impeded in that way.
As mentioned above, the use of an SOI substrate in combination with deep trenches admittedly still affords the advantage of permitting electrical insulation of the bipolar transistors without further technological expenditure. In addition the collector-substrate capacitance can be kept comparatively low. SOI substrates however suffer in particular from the disadvantage that dissipation of the heat produced in operation of the transistor is made considerably more difficult, in comparison with standard substrates. That disadvantage causes additional self-heating of the transistors under the operating conditions in the high-speed range and thus leads to a reduction in the power potential.
In addition, the Si-layers present in the case of El-Kareh et al on the buried oxide layer of the SOI substrate in a vertical configuration are too powerful to be able to produce MOS transistors which are optimised without difficulties, for example so-called ‘fully depleted MOS transistors’, on an SOI substrate. Integration of the complementary bipolar transistors with a CMOS technology which was developed for standard substrates requires additional expenditure solely because of changing over to the SOI substrate.
In the publication by M C Wilson, P H Osborne, S Nigrin, S B Goody, J Green, S J Harrington, T Cook, S Thomas, A J Manson, A Madni: ‘Process H J: A 30 GHz NPN and 20 GHz PNP complementary bipolar process for high linearity RF circuits’, pages 164-167, BCTM 1998, the use of an SOI substrate is dispensed with and the electrical insulation of the bipolar transistors in a vertical direction is achieved by means of a special insulation doping. Deep trenches are used for lateral insulation.
The arrangement put forward by Wilson et al however suffers from the decisive disadvantage that both the vertical and also the lateral interface between the collector or collector connection region and the special insulation doping contribute to the parasitic collector capacitance of the pnp-transistor. Because of the high parasitic collector capacitance, the transistor of Wilson et al is therefore unsuited to an improvement in the high-speed parameters. Furthermore the special doping used by Wilson et al requires an additional masking step.
Finally, Wilson et al, just like El-Kareh et al, involve the use of epitaxially buried collector layers and sinker dopings for the collector connection, thereby giving rise to the above-indicated disadvantages in terms of CMOS integration. That concerns in particular the fact that the epitaxially buried collectors have to be produced in the course of the process prior to the field insulation and well regions of the CMOS transistors and thus the implementation of steep profiles is greatly impeded. In this connection mention is to be made of the fact that integration of the described complementary bipolar transistors in a CMOS process is not subject-matter of the work by Wilson et al.
Therefore the technical object of the invention is to provide a complementary bipolar semiconductor device of the kind set forth in the opening part of this specification, in which both bipolar transistor types have advantageous properties for high-speed uses. A further technical object of the invention is to provide a process for the production of a bipolar semiconductor device, with which the described disadvantages of known processes can be avoided, in particular in regard to the integration of the production of the complementary bipolar transistors in a CMOS technology.